In the packaging of integrated circuits, semiconductor dies may be stacked and bonded to other package components (e.g., interposers and package substrates). The resulting packages are known as three-dimensional integrated circuits (3DICs). 3DICs have become very popular in recent years due to the increased levels of integration they provide. 3DICs typically utilize through silicon via (TSV) structures which penetrate through substrates and are employed to electrically connect features on opposite sides of the substrates.
The formation process for TSV structures at least includes etching or drilling into the substrate to form TSV openings and thinning the substrate before or after forming the TSV openings. The TSV openings are then filled with a conductive material to form the TSV structures. It would therefore be desirable to take advantage of the advanced integration levels afforded by 3DICs using TSV structures while avoiding problems created by forming such TSV structures.